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RISC-V (@risc_v) / X

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RISC-V International – RISC-V: The Open Standard RISC Instruction Set Architecture

RISC-V Bytes: Introduction to Instruction Formats · Daniel Mangum

Writing RISC-V Assembly – Stephen Marz

RZ/Five - General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz) with 2ch Gigabit Ethernet

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OnChip, SiFive Announce New RISC-V Microcontroller Cores - AB Open

Introduction — CORE-V CV32E40P User Manual documentation

RISC-V (@risc_v) / X

Instruction set of the proposed XPosit RISC-V extension.

GCC support for the draft Bit Manipulation Extension for RISC-V – Embecosm

RISC-V Foundational Associate (RVFA)

RISC-V extensions: what's available and how to find them - Red Hat Research